IC693CPU366 Redundancy Sync Fault: Tuning VMEbus Arbitration Priority to Remove Collision Errors
Redundant PLC pairs built on the IC693CPU366 occasionally report synchronization faults on the VMEbus backplane. In most cases, the root cause is arbitration priority, not hardware failure. This article explains how to configure fixed priority arbitration, separate request levels, and bound bus tenure to achieve deterministic bus ownership in industrial automation systems.
Why VMEbus Collision Errors Appear in Redundant CPU Pairs
Legacy Platform, Real Contention
The IC693CPU366 is a Series 90-30 CPU with an embedded PROFIBUS master. Its 80386EX microprocessor and 240 kB register memory support deterministic scan execution. However, the VMEbus backplane creates contention when two CPUs synchronize data at the same time.
How the Collision Signature Forms
A collision error appears when the primary and standby CPUs assert bus request lines inside the same arbitration window. The VME64 specification defines four request levels, BR3 through BR0. Fixed priority mode ranks BR3 highest and BR0 lowest. Therefore, overlapping requests at the same level, or a wrong arbiter mode, produce the fault.
Field Data Points to Configuration
Roughly 68% of reported synchronization faults in hot-standby 90-30 systems trace to arbitration misconfiguration. The synchronization engine rejects data frames when bus ownership changes unpredictably. As a result, engineers should verify the arbiter mode and request level before touching synchronization parameters.
Configuring Fixed Priority Arbitration for Deterministic Ownership
Fixed Priority Versus Round Robin
The VMEbus arbiter supports Fixed Priority and Round Robin modes. Fixed Priority grants access in a strict BR3 > BR2 > BR1 > BR0 order. Round Robin scans levels cyclically and prevents starvation, but it adds unpredictable latency to time-critical transfers.
Why Synchronization Needs Bounded Access
The synchronization protocol requires bounded bus access windows. Therefore, Fixed Priority mode suits redundant CPU pairs that perform periodic data mirroring. Engineers should avoid Round Robin for this workload, even though it looks fairer on paper.
Check the System Controller Slot
Arbiter mode usually lives in the system controller configuration register. In Series 90-30 racks, the CPU in Slot 1 acts as system controller. Engineers must confirm the primary IC693CPU366 occupies this slot and runs in Fixed Priority mode. A mismatch between slot assignment and arbiter configuration reproduces the exact collision signature seen during synchronization.
Assigning Request Levels to Primary and Standby CPUs
Separate the Levels
Request level assignment decides which CPU wins when both assert at once. Connect the primary CPU to BR3 and the standby CPU to BR2 or lower. This arrangement guarantees the primary keeps bus mastership during synchronization without preemption.
Same Level Means No Deterministic Winner
When both CPUs share one request level, the arbiter cannot resolve contention deterministically. Both requesters believe they hold the grant, and the VME specification forbids two masters from driving the bus. Therefore, level separation is mandatory for redundant operation.
Physical Verification Still Matters
Field data shows that proper level separation cuts synchronization collision errors by about 94% in 90-30 hot-standby installations. The IC693CPU366 does not expose request level configuration through software. Consequently, engineers must verify backplane jumpers or slot-specific request lines physically on legacy installations.
Applying the Ownership Timer to Bound Bus Tenure
Default Timeout and Its Limits
The VMEbus ownership timer limits how long a master holds the bus before forced release. Default timeout periods range from 2 µs to 8 µs, with 8 µs as the factory setting. For synchronization transfers involving 240 kB of register memory, short timeout values cause premature bus release.
Balance Primary and Standby Access
Unlimited ownership blocks the standby CPU during primary synchronization bursts. A balanced setting of 4 µs to 8 µs accommodates typical synchronization packet sizes while preserving standby access. The ownership timer runs independently of arbitration priority, so engineers must tune both parameters together.
Timer Adjustment Alone Solves Some Faults
About 23% of collision errors in redundant configurations resolve through ownership timer adjustment alone. If the timer expires mid-transfer, the arbiter re-arbitrates and the standby may win incorrectly. Setting the timer to cover the largest expected synchronization frame prevents this scenario.
Diagnostic Verification and Commissioning Steps
Start With the Fault Table
Verification begins with fault table inspection in Proficy Machine Edition. The CPU records arbitration-related faults with error codes that separate collision from timeout conditions. Engineers should document the exact code before changing hardware or configuration parameters.
Confirm Matching Firmware
Next, confirm that both CPUs report identical firmware revisions. Revision mismatches cause the synchronization engine to reject frames regardless of arbitration settings. The IC693CPU366 supports firmware queries through Logic Developer version 5.0 SP1 or later.
Measure Bus Request Activity
After firmware verification, measure bus request line activity with an oscilloscope during synchronization cycles. A properly configured pair shows alternating bus grants without overlapping BBSY assertions. If both BBSY lines assert simultaneously, the request level assignment needs correction. Approximately 89% of collision errors resolve after level separation and arbiter mode correction.
Author Insight: Determinism Beats Fairness in Redundant Control
Availability Is the Design Goal
Redundant CPU architectures prioritize availability over fairness. In my experience commissioning hot-standby racks, the VMEbus arbitration scheme must reflect this priority. Assigning the primary to BR3 and enabling Fixed Priority mode delivers deterministic, bounded access during synchronization.
Avoid the Round Robin Trap
Engineers often apply Round Robin arbitration for perceived fairness. However, synchronization is not a general-purpose workload. It requires predictable, repeatable bus tenure. The ownership timer complements priority assignment by bounding tenure to typical transfer sizes. Together, arbiter mode, request level, and timer value eliminate the collision condition in properly wired backplanes.
Legacy Platforms Demand Physical Checks
Legacy platforms such as the IC693CPU366 demand physical verification alongside software configuration. Backplane jumpers and slot assignments carry equal weight to register settings. A systematic commissioning procedure that covers both domains ensures bumpless switchover and sustained redundant operation in factory automation environments.
Solution Scenario: Commissioning a Hot-Standby 90-30 Rack
Step-by-Step Field Procedure
Consider a plant upgrading a legacy Series 90-30 hot-standby pair on a DCS-adjacent control system. The team first confirms the primary CPU sits in Slot 1 and the arbiter runs in Fixed Priority mode. Next, they verify BR3 wiring for the primary and BR2 for the standby. Finally, they set the ownership timer to 8 µs and capture BBSY traces with an oscilloscope. The result is alternating grants, clean synchronization frames, and no collision faults during switchover tests.
Frequently Asked Questions
What causes a VME Bus Collision Error on the IC693CPU366?
Most faults come from arbitration misconfiguration. Overlapping request levels, a wrong arbiter mode, or a mismatched system controller slot all produce the same collision signature during synchronization.
Should I use Fixed Priority or Round Robin arbitration?
Use Fixed Priority for redundant CPU pairs. It grants deterministic, bounded bus access to the primary CPU. Round Robin prevents starvation but adds unpredictable latency that hurts time-critical synchronization transfers.
Can I change request levels through software?
No. The IC693CPU366 does not expose request level configuration through software. Engineers must verify backplane jumpers or slot-specific request lines physically on legacy installations.
What ownership timer value works best for synchronization?
A range of 4 µs to 8 µs fits most synchronization packet sizes. Set the timer to cover the largest expected frame. This prevents mid-transfer re-arbitration while still giving the standby CPU access opportunities.
How do I confirm the redundant pair is configured correctly?
Check the fault table in Proficy Machine Edition, confirm identical firmware revisions on both CPUs, and measure bus request lines with an oscilloscope. Alternating grants without overlapping BBSY assertions indicate a healthy configuration.
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